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| (R) ICM7211AM Data Sheet April 17, 2006 FN3158.7 4-Digit, LCD Display Driver The ICM7211AM device is a non-multiplexed four-digit seven-segment CMOS LCD display decoder-driver. This device is configured to drive conventional LCD displays by providing a complete RC oscillator, divider chain, backplane driver, and 28 segment outputs. It also has a microprocessor compatible input configuration, which provides data input latches and Digit Address latches under control of high-speed Chip Select inputs. These devices simplify the task of implementing a cost-effective alphanumeric seven-segment display for microprocessor systems, without requiring extensive ROM or CPU time for decoding and display updating. The ICM7211AM provides the "Code B" output code, i.e., 0-9, dash, E, H, L, P, blank, but will correctly decode true BCD to seven-segment decimal outputs. Features * Four Digit Non-Multiplexed 7 Segment LCD Display Outputs with Backplane Driver * Complete Onboard RC Oscillator to Generate Backplane Frequency * Backplane Input/Output Allows Simple Synchronization of Slave-Devices to a Master * Provides Data and Digit Address Latches Controlled by Chip Select Inputs to Provide a Direct High Speed Processor Interface * Decodes Binary to Code B (0-9, Dash, E, H, L, P, Blank) * Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER ICM7211AMlM44 ICM7211AMlPL ICM7211AMlPLZ (Note) PART MARKING ICM7211AMlM44 ICM7211AMlPL ICM7211AMlPLZ DISPLAY TYPE LCD LCD LCD DISPLAY DECODING Code B Code B Code B INPUT DISPLAY TEMP. INTERFACING DRIVE TYPE RANGE (C) Microprocessor Microprocessor Microprocessor Direct Drive Direct Drive Direct Drive -40 to 85 -40 to 85 -40 to 85 PACKAGE 44 Ld MQFP 40 Ld PDIP 40 Ld PDIP* (Pb-free) PKG. DWG. # Q44.10x10 E40.6 E40.6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2004-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICM7211AM Pinouts ICM7211AM (PDIP) TOP VIEW BP g1 e1 f1 VDD 1 40 d1 39 c1 38 b1 37 a1 36 OSC 35 VSS 34 CHIP SELECT 2 33 CHIP SELECT 1 32 DIGIT ADRESS BIT 2 31 DIGIT ADRESS BIT 1 30 B3 29 B2 28 B1 27 B0 26 f4 25 g4 NC d3 g3 b4 d4 g4 f3 e3 a4 c4 e4 24 e4 23 d4 22 c4 21 b4 DATA INPUTS a2 b2 c2 d2 e2 NC g2 f2 a3 b3 c3 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 VSS CHIP SELECT 2 CHIP SELECT 1 DIGITAL ADDRESS BIT 2 DIGITAL ADDRESS BIT 2 NC B3 B2 B1 B0 f4 DATA INPUTS VDD ICM7211AM (MQFP) TOP VIEW OSC D1 SEGMENT OUTPUTS NC d1 b1 c1 a1 e1 2 g1 3 f1 4 BP 5 a2 6 b2 7 c2 8 d2 9 e2 10 g2 11 f2 12 a3 13 b3 14 c3 15 d3 16 e3 17 g3 18 f3 19 a4 20 11 23 12 13 14 15 16 17 18 19 20 21 22 Functional Block Diagram ICM7211AM D4 SEGMENT OUTPUTS D3 SEGMENT OUTPUTS D2 SEGMENT OUTPUTS 7 WIDE DRIVER 7 WIDE DRIVER 7 WIDE DRIVER 7 WIDE DRIVER 7 WIDE LATCH EN 7 WIDE LATCH EN 7 WIDE LATCH EN 7 WIDE LATCH EN PROGRAMMABLE 4 TO 7 DECODER PROGRAMMABLE 4 TO 7 DECODER PROGRAMMABLE 4 TO 7 DECODER PROGRAMMABLE 4 TO 7 DECODER DATA INPUTS 2-BIT DIGIT ADRESS INPUT CHIP SELECT 1 CHIP SELECT 2 OSCILLATOR INPUT 4-BIT LATCH ENABLE 2-BIT LATCH ENABLE ONE SHOT OSCILLATOR 19kHz FREE-RUNNING ENABLE DIRECTOR 2 TO 4 DECODER /128 BLACKPLANE DRIVER ENABLE BP INPUT/OUTPUT 2 FN3158.7 April 17, 2006 ICM7211AM Absolute Maximum Ratings Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Input Voltage (Any Terminal) (Note 1) . . . VSS - 0.3V to VDD , + 0.3V Thermal Information Thermal Resistance (Typical, Note 2) JA (C/W) Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . .-65xC to 150C Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211AM be turned on first. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CHARACTERISTICS VDD = 5V 10%, TA = 25C, VSS = 0V Unless Otherwise Specified Operating Supply Voltage Range (VDD - VSS), VSUPPLY Operating Current, IDD Oscillator Input Current, IOSCI Segment Rise/Fall Time, tr, tf Backplane Rise/Fall Time, tr, tf Oscillator Frequency, fOSC Backplane Frequency, fBP INPUT CHARACTERISTICS Logical "1" Input Voltage, VIH Logical "0" Input Voltage, VIL Input Leakage Current, IILK Input Capacitance, ClN BP/Brightness Input Leakage, IBPLK BP/Brightness Input Capacitance, CBPI AC CHARACTERISTICS Chip Select Active Pulse Width, tWL Data Setup Time, tDS Data Hold Time, tDH Inter-Chip Select Time, tICS Other Chip Select Either Held Active, or Both Driven Together 200 100 10 2 0 ns ns ns s Pins 27-34 Pins 27-34 Measured at Pin 5 with Pin 36 at VSS All Devices 4 0.01 5 0.01 200 1 1 1 V V A pF A pF Test circuit, Display blank Pin 36 CL = 200pF CL = 5000pF Pin 36 Floating Pin 36 Floating 3 5 10 2 0.5 1.5 19 150 6 50 10 V A A s s kHz Hz 3 FN3158.7 April 17, 2006 ICM7211AM Input Definitions In this table, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply. INPUT B0 B1 B2 B3 OSC DIP TERMINAL 27 28 29 30 36 CONDITIONS VDD = Logical One VSS = Logical Zero VDD = Logical One VSS = Logical Zero VDD = Logical One VSS = Logical Zero VDD = Logical One VSS = Logical Zero Floating or with External Capacitor to VDD VSS Ones (Least Significant) Twos Data Input Bits Fours Eights (Most Significant) Oscillator Input Disables BP output devices, allowing segments to be synchronized to an external signal input at the BP terminal (Pin 5). FUNCTION Interface Input Configuration INPUT DA1 DA2 DESCRIPTION Digit Address Bit 1 (LSB) Digit Address Bit 2 (MSB) Chip Select 1 Chip Select 2 DIP TERMINAL 31 32 CONDITIONS VDD = Logical One VSS = Logical Zero VDD = Logical One VSS = Logical Zero VDD = Inactive VSS = Active VDD = Inactive VSS = Active FUNCTION DA1 and DA2 serve as a 2-bit Digit Address Input DA2, DA1 = 00 selects D4 DA2, DA1 = 01 selects D3 DA2, DA1 = 10 selects D2 DA2, DA1 = 11 selects D1 When both CS1 and CS2 are taken low, the data at the Data and Digit Select code inputs are written into the input latches. On the rising edge of either Chip Select, the data is decoded and written into the output latches. CS1 CS2 33 34 Timing Diagram CS1 (CS2) CS2 (CS1) tWI tICS DATA AND DIGIT ADDRESS tDS tDH = DON'T CARE FIGURE 1. MICROPROCESSOR INTERFACE INPUT 4 FN3158.7 April 17, 2006 ICM7211AM Typical Performance Curves 30 DISPLAY BLANK, PIN 36 OPEN 25 TA = -20C 20 IOP (A) TA = 25C 15 120 150 COSC = 0pF (PIN 36 OPEN) COSC = 22pF 90 180 TA = 25C 10 TA = 70C 5 BP (Hz) 60 COSC = 220pF 30 0 1 2 3 4 VSUPP (V) 5 6 7 1 2 3 4 VSUPP (V) 5 6 FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 5 FN3158.7 April 17, 2006 ICM7211AM Description of Operation Device The ICM7211AM provides outputs suitable for driving conventional four-digit, seven-segment LCD displays. These devices include 28 individual segment drivers, backplane driver, and a self-contained oscillator and divider chain to generate the backplane frequency. The segment and backplane drivers each consist of a CMOS inverter, with the N-Channel and P-Channel devices ratioed to provide identical on resistances, and thus equal rise and fall times. This eliminates any DC component, which could arise from differing rise and fall times, and ensures maximum display life. The backplane output devices can be disabled by connecting the OSCillator input (pin 36) to VSS . This allows the 28 segment outputs to be synchronized directly to a signal input at the BP terminal (pin 5). In this manner, several slave devices may be cascaded to the backplane output of one master device, or the backplane may be derived from an external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave device represents a load of approximately 200pF (comparable to one additional segment). Thus the limitation of the number of devices that can be slaved to one master device backplane driver is the additional load represented by the larger backplane of displays of more than four digits. A good rule of thumb to observe in order to minimize power consumption is to keep the backplane rise and fall times less than about 5s. The backplane output driver should handle the backplane to a display of 16 one-half inch characters. It is recommended, if more than four devices are to be slaved together, the backplane signal be derived externally and all the ICM7211AM devices be slaved to it. This external signal should be capable of driving very large capacitive loads with short (1 - 2s) rise and fall times. The maximum frequency for a backplane signal should be about 150Hz although this may be too fast for optimum display response at lower display temperatures, depending on the display type. The onboard oscillator is designed to free run at approximately 19kHz at microampere current levels. The oscillator frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscillator free-running; the oscillator frequency may be reduced by connecting an external capacitor between the OSCillator terminal and VDD . The oscillator may also be overdriven if desired, although care must be taken to ensure that the backplane driver is not disabled during the negative portion of the overdriving signal (which could cause a DC component to the display). This can be done by driving the OSCillator input between the positive supply and a level out of the range where the backplane disable is sensed (about one fifth of the supply voltage above VSS). 6 Another technique for overdriving the oscillator (with a signal swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration shorter than about one microsecond. The backplane disable sensing circuit will not respond to signals of this duration. OSCILLATOR FREQUENCY 128 CYCLES BACKPLANE INPUT/OUTPUT 64 CYCLES 64 CYCLES OFF SEGMENTS ON SEGMENTS FIGURE 4. DISPLAY WAVEFORMS Input Configurations and Output Codes The ICM7211AM accepts a four-bit true binary (i.e., positive level = logical one) input at pins 27 thru 30, least significant bit at pin 27 ascending to the most significant bit at pin 30. It decodes the binary input into seven-segment alphanumeric "Code B" output, i.e., 0-9, dash, E, H, L, P, blank. These codes are shown explicitly in Table 1. It will correctly decode true BCD to a seven-segment decimal output. TABLE 1. OUTPUT CODES BlNARY B3 0 0 0 0 0 0 0 0 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 BO 0 1 0 1 0 1 0 1 0 1 0 1 CODE B ICM7211AM FN3158.7 April 17, 2006 ICM7211AM TABLE 1. OUTPUT CODES (Continued) BlNARY B3 1 1 1 1 B2 1 1 1 1 B1 0 0 1 1 BO 0 1 0 1 BLANK f a b g e d c CODE B ICM7211AM pin 34) are taken low. On the rising edge of either chip select input, the content of the data input latches is decoded and stored in the output latches of the digit selected by the contents of the digit address latches. An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1. The timing relationships for inputting data are shown in Figure 1, and the chip select pulse widths and data setup and hold times are specified under Operating Characteristics. The ICM7211AM is intended to accept data from a data bus under processor control. In these devices, the four data input bits and the two-bit digit address (DA1 pin 31, DA2 pin 32) are written into input buffer latches when both chip select inputs (CS1 pin 33, CS2 FIGURE 5. SEGMENT ASSIGNMENT Test Circuit VDD + - VSS 1 VDD 2 3 4 5 BP 6 7 8 EACH SEGMENT OUTPUT TO BACKPLANE WITH A 200pF CAPACITOR 9 10 11 12 13 14 15 16 17 18 19 20 DATA INPUTS DIGIT/CHIP SELECT INPUTS OSC VSS ICM7211AM 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD VDD MICROPROCESSOR VERSION MULTIPLEXED VERSION VSS FIGURE 6. 7 FN3158.7 April 17, 2006 ICM7211AM Typical Application 8 DIGIT LCD DISPLAY +5V ICM7211AM HIGH ORDER DIGITS +5V 1 VDD 2, 3, 4 SEGMENTS 6-26 35 VSS 37-40 DATA 36 OSC B0-B3 I/O ICM7211AM LOW ORDER DIGITS 2, 3, 4 1 VDD 6-26 SEGMENTS 35 VSS 37-40 36 OSC +5V 40 26 VCC VDD NC INPUT 20 P10 27 VSS 28 29 2 XTAL1 30 31 32 3 XTAL2 33 4 RESET P17 34 P20 21 7 EA 22 23 24 35 5 SS 80C48 36 COMPUTER 37 P27 38 1 TO DB0 12 13 39 T1 14 15 6 INT 16 17 18 DB7 19 RD 8 BP 5 BP 5 DATA B0-B3 DS1 DS2 CS1 CS2 27 28 29 30 31 32 33 34 DS1 DS2 CS1 CS2 27 28 29 30 31 32 33 34 I/O ALE PSEN PROG WR 11 9 25 10 FIGURE 7. 80C48 MICROPROCESSOR INTERFACE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN3158.7 April 17, 2006 |
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